1. Field of the Invention
This invention generally relates to an interrupt control circuit and in particular to an indirect type interrupt control circuit.
2. Description of the Prior Art
FIG. 2 shows in block form a direct address type interrupt control circuit (hereinafter, also referred to as a first prior art example) using a programmable interrupt controller integrated circuit model M5L8259 manufactured by Mitsubishi Electric Company. In FIG. 2, there are provided three M5L8259 integrated circuits 41 through 43 which are coupled to a central processing unit (CPU), a random access memory (RAM) and an associated peripheral circuit, which are not shown, through address, control and data buses. An interrupt request signal generated by the peripheral circuit is input into the integrated circuits 42 and 43 serving as slave controllers and an interrupt request signal output from the integrated circuits 42 and 3 is supplied to the integrated circuit 41 serving as a master controller. And, the master controller integrated circuit 41 outputs an integrated interrupt request signal to the control bus. The master controller integrated circuit 41 controls the operation of the slave controller integrated circuits 42 and 43 using signals on cascade lines CAS.sub.0, CAS.sub.1 and CAS.sub.2 to grant an interrupt to each of the circuits 42 and 43.
Alternatively, there has been proposed an indirect address type interrupt control integrated circuit model MC6828 for use in M6800 system manufactured by Motolora (hereinafter, also referred to as a second prior art example). This integrated circuit has eight interrupt input terminals and selects one of the interrupt signals input into these eight interrupt input terminals in accordance with a predetermined interrupt priority level to thereby output the thus selected single interrupt signal.
However, since the interrupt control integrated circuit of the above-described second prior art example has only eight interrupt input terminals, it cannot accept an interrupt input signal which requires more than eight interrupt input terminals. In the interrupt control integrated circuit of the first prior art example, the number of interrupt request signals may be increased by providing more slave controller integrated circuits, but this interrupt control circuit can only be used in a direct address type system and it cannot be used in an indirect address system, such as M6800 system.